1. Field of the Invention
The present invention relates to design structures, such as design structures embodied in a machine-readable medium used in a design process, the design structure including circuits, devices or methods for serial data transmission or microelectronic serial data transmitters.
2. Description of the Related Art
Data communication systems designed to operate at peak data transmission rates of 8.5, 10 or 11.1 gigabits per second (“Gbs”) or greater, are fine tuned for data transmission rate at such high transmission rate. Even though the data communication system may need to operate at lower data transmission rates, e.g., 1.5 Gbs to support various protocols such as SATA (“Serial ATA” or “Serial Advanced Technology Attachment”) and Serial Attached SCSI (“SAS”), the communication system generally is not optimized for transmission at such lower data transmission rates. To support these lower data rate, i.e., these out-of-band (“OOB”) signaling protocols, a communications system is required to perform according to stringent out-of-band (“OOB”) signaling specifications. OOB signals are low data rate signal patterns that do not appear in normal data streams. With reference to FIG. 1, OOB signals consist of leaving the output lines of the transmitter idle for idle time intervals 121, 122, 123, 124, 125 and 126 of predetermined length, followed by transmitting a signal pattern during burst intervals 111, 112, 113, 114, 115 and 116, each burst interval having a predetermined length. During the idle time intervals, the physical link between the transmitter and the receiver carries a DC idle voltage, which should equal the long term common mode voltage level of the transmitter during normal operation. During burst time intervals, the signal pattern appears on the physical link, i.e., as differential signals which rapidly transition between high and low levels at high rates, such at a rate of one or more Gbs.
Conventional data transmission systems operating at a data transmission rate of 11.1 Gbs, e.g., for Common Electrical Interconnect (“CEI”), 10 Gbs Infiniband (“IB”) or at 8.5 Gbs for Fiber Channel (“FC”) may not be able to meet the stringent OOB signaling specifications (for low data transmission rate) without degrading performance of the system at the higher 8.5, 10 or 11.1 Gbs transmission rate. The length of the DC idle time intervals for OOB signaling is predetermined, for example, as a time of 100 ns. Further, the OOB signaling specifications place a maximum limit on the amount of time required for the data communications system to transition between idle time and burst time. The transition between one burst time interval and the DC idle time interval needs to occur quickly to allow sufficient response time for an OOB signal detection circuit at the receiver to detect the transition. Slow transitions between DC idle time or burst time intervals or difficulty in detecting the transitions can cause the length of the DC idle time interval to appear to shrink, leaving less time available for OOB signaling.
The OOB signaling specifications also impose maximum deltas on voltage offset and common mode voltage for out-of-band operation. Referring to FIG. 2, OOB offset delta is the mismatch voltage offset between the final outputs of the P and N legs of a differential data transmitter. With a differential data transmitter outputting a differential pair of signals, one signal 140 of the pair of differential signals on the P leg, and another signal 142 of the pair of differential signals on the N leg, when the OOB offset delta is high, the output 142 of the N leg may appear to dip lower than the output 140 of the P leg and the output 142 of the N leg may not rise as much as the output 140 of the P leg. Alternatively, the output 140 of the P leg may appear to dip lower or not rise as high as the output 142 of the N leg. The term OOB common mode voltage delta refers to the difference between the average common mode DC voltage 150 of the signals 140, 142 when the data transmitter is transmitting during burst time intervals and the average common mode DC voltage level 152 during the DC idle time intervals.
Variations in the processing used to make microelectronic transmitters, as well as variations in the operating environment of the transmitter such as temperature or power supply voltage to which it is subjected in operation can cause the common mode voltage level output by the transmitter to vary. These variations can also cause the length of the transition time between DC idle time and burst time to vary. These variations pose additional challenges for meeting the OOB signaling specifications.
Further challenges are posed by the requirement of the OOB signaling specifications for a transmitter to begin OOB signaling quickly upon entering the OOB operational mode. The transmitter can be operating in any one of many different signaling states when it is reset to enter the OOB operational mode. For example, the transmitter can be operated in one of several different feed forward equalization (FFE) modes, be connected with a receiver and operating in AC-coupled mode or DC coupled mode, and can be transmitting with various transmitter output amplitude settings. The transmitter must be designed robustly to be reset from any of such valid transmitting states to the OOB signaling state.
A Fiber Channel protocol transmitter with out-of-band signal transmission capability is described for connection to an SATA bus in U.S. Patent Publication No. 2003/0158991 to Deyring et al. As illustrated in FIG. 3, to enable OOB signal transmission, a DC blocking capacitor 16, 18 having a predetermined value is connected in series with each of the differential signal output lines 12, 14, respectively of a transmitter 10. The conventional Fiber Channel transmitter 10 is modified with a signal generator 28 to transmit a non-data pattern signal 26 containing an unbroken string of either all ‘1’s or an unbroken string of all ‘0’s into a parallel input, serial output shift register at the transmitter input. After some time, the DC blocking capacitors cause the signals representing the unbroken string of ‘1’s or ‘0’s to decay to a long term common mode DC voltage levels at points 20, 22 of the data output lines to output a constant common mode DC voltage level during the DC idle interval. As the OOB signaling transmitter 10 (FIG. 3) relies on DC blocking capacitors to reach the DC level for the DC idle interval, the OOB signaling transmitter is only useful when it is AC coupled to a data transmission channel. Another problem of the prior art OOB signaling transmitter is that it may not meet the requirements for rapid transitioning between the DC idle time interval and the burst time interval. DC blocking capacitors such as the capacitors 16, 18 shown in FIG. 3 generally have capacitance on an order of nanofarads (nF). Given that transmitter internal termination resistance is generally set to 50Ω or possibly 100Ω, as shown in FIG. 3, an RC time constant associated with transitioning from burst state to DC idle state is on the order of about 50 nanoseconds (ns). Fifty nanoseconds transition time is too long to satisfy the quick transition detection requirements of the OOB signaling specification. However, if the amount of DC blocking capacitance is reduced to an amount lower than nanofarads, lower frequency components of the transmitter output can be excessively attenuated, making both OOB and normal data transmission more difficult.